what is Latch up?How to avoid Latch up?
Latch-up is a condition in which the parasitic components give rise to the Establishment of low resistance conducting path between VDD and VSS with Disastrous results.
View ArticleExplain Clock Skew?
When a clock is triggered, if it reaches first to destination and next to source then we have a loss of data,or if it reaches first to source and later to destination we have a wrong result .this is...
View ArticleWhat are set up time & hold time constraints? What do they signi
Setup time: Time before the active clock edge of the flipflop, the input should be stable. If the signal changes state during this interval, the output of that flipflop cann't be predictable (called...
View ArticleExplain the difference between write through and write back cache.
Write Through. After writing in cache memory, main memory is updated too inmediatly to mantain reliability Write Back After writing in cache memory a flag bit called dirty bit is set. When this value...
View ArticleExplain the concept of a Clock Divider Circuit? Write a VHDL code for
IN SPARTAN 3E BOARD.. THE INTERNAL CLOCK FREQUENCY IS 16MHZ... IF WE WANT TO INTERFACING THE EXT DIPLAY DEVICES WE WON'T RUN IT WITH A NORMAL CLOCK FREQ(16 MHZ)....THATSWHY I HAVE TO CREATED NEW CLOCK...
View ArticleImplement D flip-flop with a couple of latches? Write a VHDL Code for
library ieee; use ieee.std_logic_1164.all; entity d_ff is port(d,clk:in std_logic; q,q'bar:out std_logic); end d_ff; architecture a_d_ff of d_ff is begin process(clk) begin if rising_edge(clk) then...
View ArticleWhich gate is normally preferred while implementing circuits using CM
NAND gate is normally prefered because the mobility of holes in NAND gate is three times greater than mobility of electron.
View ArticleWhat is Noise Margin? Explain the procedure to determine Noise Margin
In digital logic design the general representation of input and output are High and low level (1's and 0's). In actual case when the input signal transitions the output switches to full swing before...
View ArticleWhat is LVS, DRC?
LVs means LAyout versus schematic -method to check the correctness of ur layout designed by cross checking with netlist generated from schematic using the tool. DRC means....??
View ArticleWhat is the most complicated/valuable program you written in C/C++?
hello world program
View ArticleDefine threshold voltage?
threshold voltage is defined as the minimum voltage that required to make the transistor ON. transistor may be either NMOS or PMOS.For NMOS the value of threshold voltage is positive value and for PMOS...
View ArticleDifferences between DRAM and SRAM?
dram consist of only one transistor and then it is a volatile memory.it is refreshed periodically otherswise stored informations are deleted. sram consists of five or six transistors and it is also a...
View ArticleDifferences between D-Latch and D flip-flop?
D-latch is level Triggering and D Flip Flop is Edge triggering.
View ArticleDifferences between functions and Procedures in VHDL?
functions are the one which conatiin some algorithm and execute in zero simulation time where as procedures may consume some simulation time when its getting executed you can compare with verilog task...
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